Huawei outlined a new scaling principle for semiconductor design, which it claims can boost performance and hardware density beyond the limits of Moore’s Law.

The Tau (τ) Scaling Law – also referred to as “Her’s Law” in recognition of He Tingbo (pronounced "Her Tingbo"), chair of Huawei’s Scientist Committee and president of its Semiconductor Business – argues that emphasis on transistor shrinking in logic development should be usurped by time scaling.

Where the longstanding Moore’s Law propagates the idea that generational hardware leaps come from gradual physical shrinking of transistors on a chip, Huawei’s idea instead contends that chip development can be improved by reducing propagation delays in chip signals – like by shortening wiring paths to allow for higher performance.

“Geometric scaling itself has always delivered time-domain gains, faster transistors, shorter response time, higher chip frequencies,” He said in a speech at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS). “This means space and time are two sides of the same coin. Losing geometric scaling does not mean losing time scaling. Time scaling is the ultimate goal that system evolution has been pursuing, continuously raising operating frequency for higher performance.”

The doctrine Huawei is trying to leave behind

Moore’s Law – coined in 1965 – argues that the number of transistors on a chip doubles roughly every two years, resulting in computing costs halving. The doctrine has long been praised as gospel in the chip design and has been routinely put to the test in recent years as current-day generational leaps are mammoth in size, with chip-level improvements buoyed by software optimizations that push performance levels even further.

But where detractors as far back as 2008 predicted the idea’s obsolescence by 2036, the reality today is that Moore’s Law-induced geometric shrinking is hitting physical limits well ahead of that timeframe.

Huawei’s Moore’s Law-busting concept then looks to improve chip designs without being able to shrink transistors further.

Where geometric shrinking already reduced the time it takes for signals to propagate through circuits, He and the Huawei team contended that hardware designers can attack the time dimension directly without needing to shrink geometry.

Huawei’s concept garners its name from the concept driving it, which is straight out of chip physics 101: τ = resistance (R) times capacitance (C), the principle that governs how fast a signal can travel through a wire or switch a transistor.

Huawei argues that by reducing the R or C anywhere in a system, be it through better materials, smarter layouts, or new architectures, the result is faster chips without needing a smaller process node.

The Chinese tech giant has been quietly employing the concept over the past few years through technologies like its LogicFolding architecture, which boosts τ performance across the device level, circuit level, chip level, and system level.

He revealed that some 381 chips have been designed and mass-produced using the τ Scaling Law, with its proprietary LogicFolding used to shorten critical-path wiring and optimize the resistance of transistors and interconnects. It was also paired with the company’s own interconnect protocols to boost memory needs for its ultra-massive data center computing line, SuperPoD.

The executive also indicated the technology has been instrumental in developing Huawei’s upcoming Kirin processor line. He suggested that the combination of LogicFolding-supported circuit-level efficiency and software optimization is projected to more than double the efficiency of the hardware within the next three to five years.

“Six years along the τ scaling path, practice has delivered excellent results,” He said. “At the circuit level: transistor density at the fabrication standard has climbed from 155 toward 240 to 300 MTr/mm² (millions of transistors per square millimeter), and approaching 400-plus rapidly. For SoC, considering a design utilization of 60 to 75 percent, effective transistor density climbed from under 100 to more than 250 MTr/mm².”

Could Huawei’s Tau help it close the gap?

There’s another part to this scaling story. Due to heavy sanctions from the US and allies, Chinese firms building chips are severely hampered by access to high-end technologies used in production. The chief of which is advanced lithography equipment from Dutch semiconductor giant ASML.

The firm is the sole supplier of extreme ultraviolet lithography (EUV) photolithography machines used to print the tiny features necessary to pack ever-shrinking transistors on a chip. But the supplier’s government backed a US-led demand to stop supplying some of its equipment to Chinese customers, severely hampering their hardware development abilities.

Beyond building its own lithography machinery, Huawei’s Tau Scaling Law sees it double down on its own engineering nous to compete with Western rivals. He said in her speech that improvements brought on by the concept would allow it to reach transistor densities equivalent to 1.4-nanometer (nm) processes.

Taiwan Semiconductor Manufacturing Co. (TSMC) is working to produce the first-generation of 2nm chips for customers, with adoption expected around early 2027, while AMD looks to be among the first to offer hardware at that level, through its forthcoming "Venice" sixth-generation EPYC processor.

But at 1.4nm, TSMC is reportedly eying mass production around 2028 – which, while earlier than Huawei’s anticipated date, would see the Chinese firm significantly close the gap on its contemporaries. Huawei CEO Ren Zhengfei last summer said its chips were now just one generation behind those made by its U.S. counterparts.

“We believe that openness and collaboration are key to driving ongoing progress in the semiconductor industry,” He said. “No single company can independently find all the answers along the path of semiconductor evolution. With the τ Scaling Law, we look forward to working closely with scientists, engineers, and industry partners around the world to drive the sustainable development of the semiconductor and electronics industries.”