TSMC will announce plans to introduce a new process node for client applications annually and a new node targeting AI and HPC every two years, according to its product roadmap through 2029.

During its 2026 North America Technology Symposium, which took place this week in San Jose, California, the company unveiled three new fabrication processes: A12 and A13, 1.2nm and 1.3nm technologies, and N2U, an extension of the chipmaker’s N2 (2nm) family.

According to TSMC, A13 is a direct shrink of its A14 node, which was unveiled by the company last year. Direct shrink is a manufacturing strategy whereby an existing chip design is scaled down onto a smaller, more advanced node, with limited architectural changes.

The area reduction of A13 will be around six percent compared to its predecessor, while “maintaining full design-rule and electrical compatibility, enabling customers to benefit with minimal redesign,” the company said. Both A13 and A12 are scheduled for production in 2029, while A14 and N2U have a production date of 2028.

A13 and A14 will target smartphones and client devices, while N2U and A12, the latter of which will feature Super Power Rail technology to provide backside power delivery, will target AI and HPC applications.

"We continue to extend our 2nm platform with N2U, which provides additional improvements in performance, power, and density through design-technology co-optimization,” said Kevin Zhang, deputy co-chief operations officer and SVP. "Our strategy is to continue enhancing each node after introduction, allowing customers to maximize the return on their design investments while still gaining incremental PPA benefits."

Alongside the introduction of the new process nodes, the chipmaker also said that all the technologies outlined on its roadmap will be manufactured using extreme-ultraviolet lithography (EUV) tools from ASML, instead of the most advanced high-NA EUV machines.

High NA EUV tools require less light per exposure than traditional EUV machines, reducing the time required to print each layer and therefore increasing wafer output. However, they also cost around double the amount of the standard EUV machines, with each unit costing approximately $370 million.

"This is where I think our R&D has done exceptionally well in terms of leveraging existing EUV technology while setting an aggressive technology scaling roadmap," said Zhang, in comments reported by Reuters. "This is definitely a strength."

TSMC breaks ground on Arizona chip packaging plant

According to a separate report from Reuters, the Taiwanese chipmaker is planning to open a chip packaging plant in Arizona by 2029, with company executives confirming during the event that construction on the facility has already begun.

TSMC’s board of directors approved the purchase of 900 acres of land in Phoenix, Arizona, during an Arizona State Land Department auction on January 7, 2026. On its earnings call that same month, the company said it was applying for permits to begin construction, but did not provide an outline of the anticipated timeline.

"We are aggressively expanding our own capability within ​the Arizona facility," Reuters reported Zhang as saying. "We are going to build a CoWoS capability and 3D-IC capability there before ​2029, so that's still our goal.”

To date, the chipmaker has invested more than $65 billion in the construction of three chip fabs in Phoenix. In March 2025, the company doubled down on its investment in the US, announcing plans to invest up to $100bn into the US chip manufacturing industry. In total, TSMC is planning to build six wafer fabs, two advanced packaging plants, and one R&D center in Arizona.