NASA is seeking bids for a high-powered server to help with "applied machine learning research towards experimental protocols."
The system will be used as part of its High Rate Delay-Tolerant Network (HDTN) Project.
In a procurement notice, the space agency said that it was seeking a 4U system with a Gigabyte G482-Z51 motherboard, two AMD Epyc 7763 CPUs (64 cores), and five Nvidia Tesla A100 GPUs. It will also include 32x 64GB 3200MHz DDR4 DIMMs, and six 1.9TB Intel SSD S4510 Data Center Series 2.5in Sata3s.
The system will be shipped to NASA's Glenn Research Center in Cleveland, Ohio, where it will help with the center's DTN research.
Delay or disruption-tolerant networking (DTN) is a store and forward protocol where information is passed from node to node and then stored when connectivity falls apart, making it perfectly suited for the latency-heavy and disruptive environment of outer space.
“In order to effectively support manned and robotic space exploration, you need communications, both for command of the spacecraft and to get the data back,” TCP/IP co-founder Vint Cerf told DCD for our feature on DTN earlier this year.
“And if you can't get the data back, why the hell are we going out there? So my view has always been ‘let's build up a richer capability for communication than point-to-point radio links, and/or bent pipe relays.’"
HDTN is a variation of DTN that the Glenn Research Center hopes to develop that could create a "high-speed path for moving data between spacecraft payloads, and across communication systems that operate on a range of different rates."
In a project note, NASA said: "The work being completed at NASA GRC is done in collaboration with NASA Marshall Space Flight Center, and will be combined with their DTN implementation, known as DTN-ME, for delivery to the [International] Space Station. Future spacecraft applications may require faster rates than the current arch texture can provide, so a hardware-accelerated version of HDTN is also under development, targeting 100-200 Gbps, using field programmable gate arrays."