Synopsys and TSMC have partnered to accelerate the development of next-generation AI chips and multi-die designs.

The collaboration will allow TSMC to deliver multi-die solutions using Synopsys’ advanced EDA (electronic design automation) and IP offerings, supporting TSMC’s leading-edge processes and packaging technologies that are helping to drive innovations in AI chip design, the companies said.

Synopsys and TSMC have worked together for more than 20 years, during which time the two companies have jointly delivered multiple EDA and IP solutions for TSMC's advanced processes and advanced packaging technologies.

Included in the latest round of offerings from Synopsys are its 3DIC Compiler exploration-to-signoff platform and IP. The platform, which has been tuned for 3D packaging, has already resulted in multiple tape-outs from TSMC customers using the chipmaker’s advanced 3D stacking and CoWoS packaging technologies.

Additionally, the company’s new AI-assisted design flow for TSMC COUPE uses Ansys optiSLang and Ansys Zemax OpticStudio software to shorten development times and strengthen design quality, while the companies’ ongoing silicon photonics collaboration has enabled an AI-optimized photonic IC flow for TSMC-COUPE technology, delivering enhanced system performance and addressing multi-wavelength and thermal requirements in multi-die and AI designs, they claim.

Synopsys also provides EDA, IP, and multiphysics simulation solutions for TSMC’s most advanced process nodes and packaging technologies: A16, N2P, N3P, N3C, and NanoFlex, meaning the company offers the “broadest portfolio of silicon-proven IP across TSMC nodes,” ranging from 16nm to 2nm, and now including new certified IP for the NP2/N2X processes.

Synopsys announced it had first achieved first-pass silicon success using TSMC’s N2 process and certified digital and analog EDA flows for TSMC’s A16 and N2P technologies in April 2025, a move which, at the time, the company said represented a “major step forward in the development of next-generation AI-enabled systems,” adding that the success would help accelerate the industry’s transition from FinFET to nanosheet architecture, supporting increased chip performance and power efficiency.

TSMC and Synopsys will further partner on the design flow development for TSMC's A14 process, with its first process design kit release scheduled for the latter part of 2025.

"Our close collaboration with TSMC continues to empower engineering teams to achieve successful tape outs on the industry's most advanced packaging and process technologies," said Michael Buehler-Garcia, SVP at Synopsys. "With certified digital and analog EDA flows, 3DIC Compiler platform, and our comprehensive IP portfolio optimized for TSMC's advanced technologies, Synopsys is enabling mutual customers to deliver differentiated multi-die and AI designs with enhanced performance, lower power, and accelerated time to market."

Aveek Sarkar, director of the ecosystem and alliance management division at TSMC, added: “TSMC has been working closely with our long-standing Open Innovation Platform® (OIP) ecosystem partners like Synopsys to help customers achieve high quality-of-results and faster time-to-market for leading-edge SoC designs," said "With the ever-growing need for energy efficient and high-performance AI chips, the OIP ecosystem collaboration is crucial for providing our mutual customers with certified EDA tools, flows, and high-quality IP to meet or exceed their design targets."