A Silicon Valley company that develops semiconductor technologies has announced a new platform it says will dramatically reduce power consumption of integrated circuits, while keeping performance levels stable.

SuVolta's new PowerShrink platform slashes power consumption of complementary metal oxide semiconductors (CMOS) at least in half, according to the company's news release. The platform consists of the firm's Deeply Depleted Channel (DDC) CMOS transistor technology, DDC-optimized circuits and design techniques that take advantage of DDC transistor properties.

The platform enables a reduction in supply voltage by 30% or more, which is what cuts active power consumption. It also reduces power leakage by 80% or more.

In the same announcement, SuVolta said Fujitsu's semiconductor arm has licensed its new technology.

SuVolta CTO Scott Thompson said in a statement that while innovation in semiconductor process technology has up until now focused on increasing performance, power was the biggest problem in semiconductors today.

"SuVolta is solving the power impasse by significantly reducing transistor threshold voltage variation and therefore enabling supply voltage scaling," he said. "SuVolta's DDC sub-micron technology addresses threshold voltage control by limiting random and other sources of dopant fluctuation while simultaneously improving carrier mobility and reducing device capacitance so as to maintain circuit speed at much lower power."

The platform is compatible with existing manufacturing and design infrastructure, with its transistor leveraging existing CMOS design rules and process flows.