The Mont-Blanc European project will use Cavium’s ThunderX2 ARM-based server processor to power its High Performance Computing prototype.

The project aims to design an Exascale-class compute node based on the ARM architecture - which has increasingly been adopted by organizations in the supercomputing field.

A mountain of computing power

Mont Blanc
– Wikimedia Commons/Zoharby

“ThunderX2 is a server-class chip designed for high compute performance,” Etienne Walter, coordinator of phase 3 of the Mont-Blanc project, explained.

“With the adoption of this new generation of power- and performance-efficient processors, we are entering a new and exciting dimension of the Mont-Blanc project. This already gives us a glimpse of what a European exascale-class HPC platform could be in the near future.”

The prototype will be built by French IT giant Atos, using parts of its Bull ’sequana’ pre-exascale supercomputer range for network, management, cooling, and power.

Rishi Chugh, director of marketing for Data Center Processor Group at Cavium, added: “As the race to Exascale intensifies, we are pleased to be the vendor of choice to partner with Atos to deliver Mont-Blanc platform.

“ThunderX2 builds on established architecture and ecosystem of ThunderX delivering performance competitive with next generation of incumbent processors.”

The ThunderX2 range consists of Cavium’s second generation workload-optimized 64-bit ARMv8-A systems-on-a-chip (SoCs). It can fit up to 54 cores on a single die, with up to 3.0 GHz core frequency, and includes six DDR4 72-bit memory controllers that can run at 3200 MHz, supporting up to three Terabytes of memory in a dual socket configuration. 

Mont-Blanc will serve as an Alpha-site for ThunderX2.