Intel plans to acquire structured application-specific integrated circuit (ASIC) designer eASIC for an undisclosed sum.

Structured ASICs are seen as an intermediary technology between FPGAs and ASICs, with performance and power efficiency close to standard-cell ASICs, but with the faster design time and lower non-recurring engineering costs that are more akin to FPGAs (field-programmable gate arrays).

eASIC will join Intel’s Programmable Solutions Group (PSG), which also includes Altera, the FPGA company Intel bought for $16.7bn in 2015. Subject to customary closing conditions, the deal is expected to be completed in the third quarter of 2018.

Converting from FPGAs

Intel logo
– Sebastian Moss/DCD

“Having a structured ASICs offering will help us better address high-performance and power-constrained applications that we see many of our customers challenged with in market segments like 4G and 5G wireless, networking and IoT,” Dan McNamara, corporate VP and GM of Intel’s PSG, said in a blog post.

“We can also provide a low-cost, automated conversion process from FPGAs (including competing FPGAs) to structured ASICs.”

He added: “Longer term, we see an opportunity to architect a new class of programmable chip that takes advantage of Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology to combine Intel FPGAs with structured ASICs in a system in package solution. Together with partners and customers, Intel and eASIC expect to deliver industry-leading solutions.”

Intel collaborated with eASIC in the past - the pair announced they would develop custom server solutions for cloud providers together back in 2015.

“The eASIC team has developed and deployed a truly innovative structured ASIC product,” Ronnie Vasishta, president and CEO of eASIC, said.

“The marriage of the eASIC technology with IP and capabilities of Intel will allow the ubiquitous deployment of this proven structured ASIC product into a wide breadth of exciting end applications and markets. This is the perfect time to usher in this new chapter for eASIC.”