Google is reportedly working with AMD for the development of its tenth-generation TPUs (Tensor Processing Units), according to analysts from SemiAnalysis.

“Market chatter suggests Google is working with AMD on a TPU project in the v10 generation,” per a report from the research firm that was shared on social media. “AMD’s involvement would be the first real involvement in a custom AI ASIC project, despite having a custom silicon team.”

The post went on to note that “AMD has strong IP, especially in advanced packaging and SoIC. Additionally, CPU IP could also be a draw given Google and its customers are pushing for TPUs with on-package CPU cores for RL (reinforcement learning) workloads."

The rumor was disclosed alongside market data from SemiAnalysis that stated it was seeing “lower TPU output in 2H26 than previous expectations,” which the firm attributed to challenges ramping up capacity for CoWoS-S (Chip-on-Wafer-on-Substrate-Silicon) advanced packaging.

“For 2027, we also see lower TPU output than our previous expectation of 6 million units of TPU 7 and TPU8i. This is driven by greater allocation towards other customers.” According to the post, units of Google v7 TPU, dubbed Ironwood, were revised down from 3.2 million units to 2.7 million units, with Broadcom cutting its total 2026 CoWoS wafer output from 250,000 wafers to 215,000 wafers.

Google began development of its TPU v1 in 2013, before deploying the processing internally in 2015. The chip was publicly unveiled at Google I/O in May 2016, and made available for external cloud customers in 2018.

In April 2026, Broadcom stated in a regulatory filing that it had entered into a Long-Term Agreement with Google to develop and supply future generations of its TPUs, in addition to signing a Supply Assurance Agreement to supply “networking and other components” to be used in Google’s next-generation AI racks until 2031.

Two weeks after that announcement, Google unveiled the eighth generation of its Tensor Processing Units (TPUs), consisting of two chips dedicated to AI training and inference workloads.

Dubbed the TPU 8t (for training) and the TPU 8i (for inference), Google said the hardware was designed in partnership with Google DeepMind and has “purpose-built architectures” to support model training, agent development, and inference workloads.

Following the publication of the hyperscaler’s Q1 2026 results, Google said it was planning to offer its TPUs to a “select group of customers” for deployment in their own data centers.