The Gen-Z consortium has shared the full version of an open standard developed to enable high bandwidth, low latency connections between CPU cores and system memory.
The consortium envisions a future where servers are equipped with Terabytes of memory, something that’s required to efficiently process resource-intensive workloads in emerging fields like advanced analytics and machine learning.
Gen-Z involves most of the major names in chip design and manufacturing, with the notable exception of Intel.
Gen-Z was established in 2016 to create a new architectural standard that would eliminate the bottlenecks between processors and memory. Its members include AMD, ARM, Broadcom, Cavium, Cray, Huawei, IBM, Micron, Qualcomm, Samsung, SK hynix and Xilinx.
The consortium says Gen-Z Core Specification 1.0 enables silicon providers and IP developers to begin the development of products enabling Gen-Z technology solutions.
Along with traditional memory, the standard supports Storage Class Memory (SCM) – also known as persistent or non-volatile memory - new types of RAM that can store information even after the system has been switched off.
“Our membership has grown significantly throughout 2017, now totaling more than fifty members, and we are proud of the hard work that has culminated with the release of our first Core Specification,” said Gen-Z president, Kurtis Bowman.
“We anticipate great things in 2018 as silicon developers begin implementing Gen-Z technology into their offerings and the ecosystem continues to grow.”