Archived Content

The following content is from an older version of this website, and may not display correctly.

Chip maker AMD has redesigned its CPU cores so that servers can cope better with the modern mix of content that has to be processed.

At its Core Innovation Update conference in San Francisco, the company unveiled Seattle, its first 64bit ARM processor, and pledged to continue developing the x86 chip design.

Both the ARM and x86 architectures will be the bridges to the future, said AMD’s general manager of global business units Lisa Su.

AMD announced that it has become an ARM architectural licensee and is developing its own ARM cores for a future in which data centers will be increasingly involved in embedded, server, client and semi-customised business.

Patrick Moorhead, principal analyst at Moor Insights & Strategy, predicted that AMD's designs could yield hardware R&D cost savings for server makers.

The chipmaker unveiled Project SkyBridge which it described as an ‘ambidextrous design framework’ consisting of pin compatible 64bit ARM and x86 processors.

The x86 SkyBridge products will use AMD’s Puma+ cores, which were first announced with the Beema and Mullins accelerated processor units. It will have full heterogenous system architecture (HAS) support.

In the ARM range of processor the low-power A57 64bit ARM Cores will be launched as AMD's first HSA Android platform.

“There is a fundamental disruption in the server market over the next few years,” Su said.

“That’s why we chose a 64bit ARM chip.”

AMD argued that the workload for many data centers is changing the types of processor needed in servers.

In a demo, it showed an increasingly typical operation for a server, according to its research, which involved a 28nm 64bit ARM server processor driving a server running a WordPress blog and playing video on the fly.

Seattle, AMD’s new ARM server architecture, can have up to 8 ARM Cortex A57 cores and up to 4MB shared L2 and 8MB L3 cache, said Su. It can store up to 128GB per core and features dual channel DDR3/4 with ECC up to 1866MHz.

According to Su, AMD’s ‘ambidextrous strategy’ for servers involved developing 64bit ARM cores in conjunction with new 64bit x86 cores.