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Cavium and IDT want to ARM hyperscale data centers

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Collaboration for a low-energy high performance platform design adds IDT’s memory to ThunderX

ARM processor specialist Cavium has added memory access technology from IDT to system designs for Open Compute Project (OCP) servers intended for hyperscale data centers. 

Cavium will include the DDR4 memory chipset from IDT (Integrated Device Technology) in the ARM ThunderX reference design for hyperscale data centers. ThunderX is Cavium’s family of 64-bit v8 CPUs based on the ARM core. 

ThunderX SoC

Source: Cavium

OCP unites industry

Cavium has partnered with other vendors, including Microsemi, which provides the HBA 1000 Host Bus Adaptor for ThunderX platforms, but the IDT announcement goes further, including IDT’s DDR4 chipset in the Cavium reference design for ThunderX servers created for the Open Compute Project and hyperscale facilities.

The DDR4 chipset from IDT enables registered DIMMs (RDIMMs), load-reduced DIMMs (LRDIMMs), and unbuffered dual inline memory modules (UDIMMs) covering the complete range of memory necessary for next generation computing needs in the data center.

Commenting on how IDT’s active presence in the OCP High Performance Computing Project made it a good partner, given Cavium’s own work with the OCP, Rishi Chugh, director, data center processors at Cavium, said: “Our relationship with IDT enables us to deliver workload-optimized, flexible, scalable and efficient ARM-based server solutions to the data center market, including the growing community of the OCP.”

The current generation ThunderX2 processors integrate 100Gbps of IO bandwidth with integrated 25GBPS SerDes and six DDR4 72-bit memory controllers with support for more than one TB of memory at 3200 MHz in a dual-socket configuration. The SoC supports up to 54 cores in a single socket at up to 3 GHz core frequency. The ThunderX2 family offers multiple SKUs optimized for different workloads and common data center operations, such as compute, networking, and storage.

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