Cookie policy: This site uses cookies (small files stored on your computer) to simplify and improve your experience of this website. Cookies are small text files stored on the device you are using to access this website. For more information on how we use and manage cookies please take a look at our privacy and cookie policies. Some parts of the site may not work properly if you choose not to accept cookies.

sections

ARM boosts supercomputing potential with long vector support

  • Print
  • Share
  • Comment
  • Save

Fujitsu will use the new Scalable Vector Extension (SVE) functionality to build the world’s fastest computer

British chip designer ARM is working to improve its ARMv8-A architecture in order to make the silicon more suitable for demanding data center workloads and High Performance Computing (HPC) applications.

The addition of Scalable Vector Extension (SVE) functionality will increase parallelization of program execution, helping run complex calculations faster.

SVE was developed in partnership with Fujitsu – the Japanese company will be using ARM chipsets to build its upcoming supercomputer, set to become the most powerful computer on the planet once it is switched on in 2020.

Support for SVE was announced at the Hot Chips symposium in California on Monday.

For science

CPU chip blueprint

Source: Thinkstock / Icon_Craft_Studio

SVE improves the vector processing capabilities associated with 64-bit ARM architecture to enable vector lengths that scale from 128 to 2048 bits in 128-bit increments.

It is intended to enhance the ARM NEON instruction set that’s been in use for the past 12 years. NEON was developed for general purpose computing and is limited to 128-bit vector registers.

Lead ISA Architect and ARM Fellow Nigel Stephens explained in a blog post that SVE will help extract more fine-grained parallelism from existing code and so reduce software deployment effort.

“Rather than specifying a specific vector length, SVE allows CPU designers to choose the most appropriate vector length for their application and market, from 128 bits up to 2048 bits per vector register,” Stephens said.

“SVE also supports a vector-length agnostic (VLA) programming model that can adapt to the available vector length. Adoption of the VLA paradigm allows you to compile or hand-code your program for SVE once, and then run it at different implementation performance points, while avoiding the need to recompile or rewrite it when longer vectors appear in the future. This reduces deployment costs over the lifetime of the architecture; a program just works and executes wider and faster.”

The engineer added that it will take time for SVE compilers and the rest of the software ecosystem to mature. But even while scientific computing is currently leading the way, a growing need for longer vectors is expected in other areas of computing in the future.

General specification for SVE is expected in late 2016 or early 2017.

Have your say

Please view our terms and conditions before submitting your comment.

required
required
required
required
  • Print
  • Share
  • Comment
  • Save

Webinars

More link